1. Field of the Invention:
The present invention relates to a logic circuit having a self-test function. Particularly, this invention relates to a logic circuit having a self-test function for checking conditions of a high-speed logic circuit such as a flip-flop in examination of malfunctions through test scanning, program debugging, etc.
2. Discussion of the Background:
Logic circuits such as processors require a dedicated built-in self-test circuit to perform test scanning for checking operational conditions or debug programs installed therein, for failure diagnosis. In other words, operational conditions of these circuits cannot be detected without the built-in self-test circuit.
Nevertheless, the logic circuits become bulk as a larger-scale built-in self-test circuit is used. In addition, the frequency of test output signals from the built-in self-test circuit have to be converted into a low frequency when the test output signals are sent out from the logic circuits.
Therefore, the built-in self-test circuit cannot offer accurate testing in terms of circuit scale and output-signal frequency.
Known logic circuits are equipped with scanning flip-flops (F/F), such as shown in FIG. 6, for test scanning. These F/F circuits are used in checking, for example, LSI (Large Scale Integrated Circuit) equipped with flip-flops, before shipment.
In FIG. 6, a test scanning circuit 20 is equipped with scanning F/F circuits 21, 22 and 23. Each F/F circuit has a clock input terminal SCK via which a scanning clock signal C1 sent via a common clock input terminal 24 is input.
The first-stage scanning F/F circuit 21 is further equipped with a scanning input terminal SIN for receiving a scanning input signal S1 sent via an external scanning-input terminal 25 and a scanning output terminal SOUT for supplying a scanning output signal to the second-stage scanning F/F circuit 22 after a specific logic operation based on the scanning input signal S1 and the scanning clock signal C1.
The second-stage scanning F/F circuit 22 is also equipped with a scanning input terminal SIN for receiving the scanning output signal from the scanning output terminal SOUT of the first-stage scanning F/F circuit 21 and a scanning output terminal SOUT for supplying a scanning output signal to the third-stage scanning F/F circuit 23 after a specific logic operation based on the scanning output signal from the first-stage scanning F/F circuit 21 and the scanning clock signal C1.
The third-stage scanning F/F circuit 23 is also equipped with a scanning input terminal SIN for receiving the scanning output signal from the scanning output terminal SOUT of the second-stage scanning F/F circuit 22 and a scanning output terminal SOUT for outputting a scanning output signal via an scanning output terminal 26 of the test scanning circuit 20.
In the test scanning circuit 20 configured as described above, the scanning input signal S1 supplied to the scanning input terminal SIN of the first-stage scanning F/F circuit 21 is further supplied to the scanning input terminal SIN of the third-stage scanning F/F circuit 23 via the second-stage scanning F/F circuit 22, and output from the scanning-output terminal SOUT of third-stage F/F circuit 23 to the scanning output terminal 26.
In other words, the known test scanning circuit 20 externally activates the internal F/F circuits with the scanning clock signal C1 and determines whether a test signal output from the scanning output terminal 26 is equal or close to an anticipated signal, thus diagnosing the internal F/F circuits.
Not only the three scanning F/F circuits shown in FIG. 6, the known test scanning circuit 20 may perform a scanning test with four or more scanning F/F circuits which may be divided into groups.
The known logic circuits require the built-in self-test circuit to perform test scanning for checking operational conditions or debug programs installed therein.
The scale of the built-in self-test circuit is, however, limited for saving the total circuit area. In addition, the known logic circuits require signal-frequency conversion for outputting the results of internal high-speed logic operations.
These are major factors causing difficulties in producing logic circuits with a dedicated built-in self-test circuit.
Scanning tests are performed before shipment for logic LSI products having scanning F/F circuits for detecting internal malfunctions.
The known built-in self-test circuit requires a test scanning signal externally input to the scanning F/F circuits for comparison with an anticipated signal in detection of malfunctions, thus cannot be used for program debugging.